1. Field of the Invention
The present invention relates to a memory card which stores attribute data associated with itself, and more particularly and, to the internal structure of that memory card.
2. Description of the Related Art
FIG. 6 is a block diagram of the internal structure of a conventional memory card of the above-described type.
Reference numeral 1 denotes a control circuit; reference numeral 2 denotes a volatile memory element, such as an SRAM (static random access memory), for storing data. Reference numeral 3 denotes a nonvolatile memory element, such as an EEPROM (electrically erasable programmable read only memory), for storing attribute data. Reference numerals 4 and 5 denote diodes for preventing reverse flow of a current. Reference numeral 8 denotes a primary cell for supplying power to back up the memory element. Reference numerals 9 and 21 denote bypass capacitors. Reference numerals 11 and 12 denote pull-up resistors. Reference numeral 13 denotes a card enable signal line (CE). Reference numeral 14 denotes a memory selection signal line (REG). Reference numeral 15 denotes a readout control signal line (OE). Reference numeral 16 denotes a write control signal line (WE). Reference numeral 17 denotes an address signal line (An). Reference numeral 18 denotes a data signal line (Dm). Reference numeral 19 denotes a power line (Vcc). Reference numeral 20 denotes a grounded line (GND). Reference numeral 22 denotes an internal power line. An address signal (An) and a data signal (Dm) may generally be n-bit and m-bit parallel signals, respectively. The address signal line (An) 17 and the data signal line (Dm) 18 form an address bus and a data bus, respectively. A power source 50, indicated by a circle in the figure, indicates a potential of a power source line 19 which is not backed up with a battery-power supply. A power source 51, indicated by a square, indicates a potential of the internal power source line 22 which is backed up by the primary cell 8.
The operation of the memory card arranged in the manner described above will now be described. The basic read and write operations of the above-described type of memory card are disclosed in, for example, "IC Memory Card Guideline" (by Japanese Electronic Industry Development Association), and detailed description thereof will be omitted. The circuit employed in this memory card is a negative logic (low active) circuit. The operation of the memory card requires application of a voltage between the power source line .multidot.and the grounded line 20 and supply of a data signal, an address signal and various control signals to the memory card. When the memory card is connected to an external device (not shown), a voltage is applied between the power source line 19 and the grounded line 20 from the external device, and the data signal, the address signal and various control signals are input to the memory card to operate the memory card. When the card enable signal line 13 goes low under conditions that the memory card is connected to the external device and that a voltage is thereby applied to the memory card, the memory card enters the operable state. When the readout control line 15 goes low and the write control line goes high, the data stored in either of the memory elements 2 and 3 at an address corresponding to the address signal (An) on the address signal line 18 shows up on the data signal line 18. Conversely, when the readout control line 15 goes high and the write control line 16 goes low, the data (Dm) on the data signal line 18 can be written into either of the memory cards 2 and 3 at an address corresponding to the address signal (An) on the address signal line 17. The memory element to which readout or write is performed is selected by a memory selection signal (REG) on the memory selection signal line 14. If the memory selection signal (REG) is, for example, high, the memory element 2 is selected. If the memory selection signal is low, the memory element 3 is selected. More specifically, if the memory selection signal (REG) is high, the control circuit 1 supplies a low-level signal to the memory element 2 to set it in the operable state. If the memory selection signal (REG) is low, the control circuit 1 supplies a low-level signal to the memory element 3 to set it in the operable state. The memory selection signal (REG) may be the most significant bit of the address signal.
When the card enable signal line 13 goes high, both of the memory elements 2 and 3 enter the non-operating state. Consequently, power consumption is very low, and the data signal line 18 enters a high impedance state.
When no voltage is applied between the power source line 19 and the grounded line 20, e.g., when the card is not connected to the external device, a voltage is supplied from the primary cell 8 to the memory element 2 through the diode 4 to hold the data in the memory element 2. At that time, since the card enable signal line 13 is connected, through the pull-up resistor 11, to the power source 51 which is backed up by the primary cell 8, it goes high, setting both the memory elements 2 and 3 in the non-operating state.
Normally, the volatile memory element 2 is used as a data area for storing data, and the non-volatile memory element 3 is used as an attribute data area for storing the attribute data on the card. The attribute data includes physical data, such as the memory capacity of the memory card and the access time thereof, and is preferably stored in the non-volatile memory element. Normal data requires high-speed read out and write, and is preferably stored in the volatile memory element.
A non-volatile memory used in the conventional memory card arranged in the manner described above as the non-volatile memory element for storing attribute data, such as an EEPROM which can be reprogrammed after erasing data stored in it, generally requires a long writing time and is expensive.